超越 Google的晶片擺置演算法彈性
聯發科、至達科技與臺大合作論文獲選為頂尖會議DAC大會宣傳論文
Best VLSI Floorplan Solution
EfficientConsider macro and standard cell
Reduce project runtime Explore different style and objective |
EffectiveShorten routed wire length
Reduce timing violation Improve routability |
Faster Runtime
GPU accelerated placement: 20X speedup
10 million cells in 10 minutes
10 million cells in 10 minutes
* NVIDIA GeForce 1080Ti ; Intel i9-9900K
Macro Handcrafted Style
Consider regularity to improve power plan and congestion

Floating macro style
Customized Automation
Provide unique customized automation for best solution
Reduce 30% wire length on specific layout styles
Reduce 30% wire length on specific layout styles
Products to Accelerate APR Flow
Solutions for prototyping and macro placement