MAXEDA 至達科技

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Product 

MaxFlow 
MaxPlace
Contact us for more details: support @ maxeda.tech

MaxFlow: Data Flow Analyzer

Explore connectivity and timing paths to identify critical nets
Generate readable graphs and constraints for placement/floorplanning
Integrate with MaxPlace to perform dataflow-driven auto macro placement
Highlights
  • Analyze logic connectivity
  • Analyze timing information
  • Identify data flow by pins, macros, hierarchy modules
  • Analyze multi-level design hierarchy data flow 
  • Create scale vector graph
  • Review between data flow graph and layout canvas
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MaxPlace

MaxPlace is a VLSI physical design platform supporting large-scale design netlist
A high speed cell placer and a global routing based congestion predictor are included
Highlights
  • State-of-the-art cell placer to create cell placement efficient and effectively
  • Fast global-routing-based congestion predictor to estimate design routability
  • Compact database to handle 100+ million instances netlist
  • Automatic macro placer
  • Design prototyping and floorplan exploration
Features
  • Support Tcl 
  • Support LEF cell library and liberty timing library
  • Support verilog netlist, DEF netlist and floorplan, SDC design constraints
  • Support fence-region constraints
  • View placement graphically of hierarchy modules and routing congestion map
  • Display flight line nets among cells
  • Export placement DEF to exchange data with other tools
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Circuit Source: iccad15_superblue1
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MaxPlace Automatic Macro Placer

Create high quality macro placement automatically based on the state-of-the-art automatic macro placement technology
Explore quality of different design topology with high speed routability analyzer and early timing analyzer
Highlights
  • Design hierarchy-awareness 
  • Global-routing-based routability optimization
  • Various user constraints to generate flexible results
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MaxPlace Design Floorplanner

Plan hierarchy modules for global interconnect
​Data-flow awareness floorplanning to achieve better timing and routability
Highlights​
  • Interconnect wire length minimization
  • Feedthru route minimization
  • Hierarchy pin planning by global routing
  • Fast early timing analysis to identify critical paths
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    Product Inquiry

    If you have any question, please fill out the following form and we will contact you as soon as possible.
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Copyright © 2021

Maxeda Technology Inc.
14F-6, No. 27, Guanxin Rd.
​Hsinchu, Taiwan 300
​TEL: +886-3621-4888
​support@maxeda.tech
至達科技股份有限公司
300​新竹市東區
​關新路27號14樓之6
03-621-4888
support@maxeda.tech


Photo used under Creative Commons from yellowcloud