MaxFlow
MaxPlace

MaxFlow

Dataflow Extractor, Analyzer, and Visualizer
Explore connectivity and timing paths to identify critical nets
Generate readable graphs and constraints for placement/floorplanning
Integrate with MaxPlace to perform dataflow-driven auto macro placement
Highlights
  • Analyze logic connectivity
  • Analyze timing information
  • Identify dataflow by pins, macros, hierarchy modules
  • Analyze multi-level design hierarchy dataflow 
  • Create scale vector graph
  • Review between dataflow graph and layout canvas

MaxPlace

Mixed-Size Placer, Macro Packer, and Floorplan Exploration
MaxPlace is a VLSI physical design platform supporting large-scale design netlist
A high speed cell placer and a global routing based congestion evaluator are included
Highlights
  • State-of-the-art cell placer to create cell placement efficiently and effectively
  • Fast global-routing-based congestion evaluator to predict routing violations
  • Compact database to handle 100+ million instance netlist
  • Automatic macro placer
  • Design prototyping and floorplan exploration
Features
  • Support Tcl 
  • Support LEF cell library and liberty timing library
  • Support Verilog netlist, DEF netlist and floorplan, SDC design constraints
  • Support fence-region constraints
  • View placement graphically of hierarchy modules and routing congestion map
  • Display flight line nets among cells
  • Export DEF and Tcl to exchange data with other tools
Contact us for more details: support @ maxeda.tech