MAXEDA 至達科技

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MaxPlace 

MaxPlace

Mixed-Size Placer, Macro Packer, and Floorplan Exploration
MaxPlace is a VLSI physical design platform supporting large-scale design netlist
A high speed cell placer and a global routing based congestion predictor are included
Highlights
  • State-of-the-art cell placer to create cell placement efficiently and effectively
  • Fast global-routing-based congestion evaluator to predict routing violation
  • Compact database to handle 100+ million instance netlist
  • Automatic macro placer
  • Design prototyping and floorplan exploration

​Features
  • Support Tcl 
  • Support LEF cell library and liberty timing library
  • Support Verilog netlist, DEF netlist and floorplan, SDC design constraints
  • Support fence-region constraints
  • View placement graphically of hierarchy modules and routing congestion map
  • Display flight line nets among cells
  • Export DEF and Tcl to exchange data with other tools
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Circuit Source: iccad15_superblue1
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MaxPlace applies dataflow analysis & extraction, mixed-size (macros and std-cells) layout prototyping, and detailed macro & cell placer to generate high quality placement result that optimizes wire length, routability, dataflow, timing, and regularity.

Additional user constraints can be specified to further control placement results.
  • Region/group
  • Array
  • Proximity
  • Spacing
  • Alignment
  • Relative position


Automatic Macro Placer

Create high quality macro placement automatically based on the state-of-the-art automatic macro placement technology
Explore quality of different design topology with high speed routability analyzer and early timing analyzer
Highlights
  • Design hierarchy awareness 
  • Global-routing-based routability optimization
  • Various user constraints to generate flexible results
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Design Floorplanner

Plan hierarchy modules for global interconnect
​Dataflow awareness floorplanning to achieve better timing and routability
Highlights​
  • Interconnect wire length minimization
  • Feedthru route minimization
  • Hierarchy pin planning by global routing
  • Fast early timing analysis to identify critical paths
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Exploration Technology
Provide various recipes to explore trade-off among different objectives (routability, timing, density, etc.)
Automatically evaluate results and generate reports.
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Highlights
  • Reduce development cycle by exploring all possible results at once
  • Recipe and configuration are flexible
  • Filter solution effectively
  • Generate reports with customized contents
  • Provide QoR metrics (density, overflow, wirelength, TNS, etc.)  and snapshots in report
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Better Routability
MaxPlace can reduce 85% routing overflow on average using DAC/ICCAD 2012 benchmarks
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Copyright © 2021

Maxeda Technology Inc.
14F-6, No. 27, Guanxin Rd.
​Hsinchu, Taiwan 300
​TEL: +886-3621-4888
​support@maxeda.tech
至達科技股份有限公司
300​新竹市東區
​關新路27號14樓之6
03-621-4888
support@maxeda.tech


Photo used under Creative Commons from yellowcloud